1. Field of the Invention
The present disclosure relates to a display device, and more particularly, to a source driver integrated circuit that minimizes voltage level deviation of each power supplied to a plurality of channels in a display panel and optimizes an image of the display panel, and a display device including the source driver integrated circuit.
2. Description of the Related Art
FIG. 1 illustrates an embodiment of a conventional display device.
Referring to FIG. 1, the conventional display device includes a printed circuit board (PCB) 100 that controls the entire operation of the display device, a display panel 360 in which a plurality of pixels are two-dimensionally arranged, source driver integrated circuits 320 and 340 that control the operation of the display panel 360 as COG (Chip On Glass), and a flexible printed circuit board (FPCB) 200 that electrically connects the PCB 100 to the source driver integrated circuits 320 and 340 by using LOGs (Line on Glasses) 301, 302, 303, and 304.
Among them, the source driver integrated circuits 320 and 340 and the display panel 360 are installed on a panel glass 300, and the PCB 100 and the source driver integrated circuits 320 and 340 are electrically connected to each other by using the LOGs 301, 302, 303, and 304.
The display panel 360 includes a plurality of channels Chc, Chc+1, Che, and Che+1, and power is supplied to the respective channels Chc, Chc+1, Che, and Che+1 through respective metal lines 305 to 310. The metal lines 305 to 310 electrically connect pads 323 to 326 and 343 to 346 for outputting panel driving signals to the plurality of channels Chc, Chc+1, Che, and Che+1, and may be LOGs.
Referring to FIG. 1, it can be understood that the lengths of supply paths P11, P12, P13, and P14 of the panel driving signals supplied to two adjacent channels Chc and Chc+1 or Che and Che+1 are equal to each other. This is because two pads 321 and 322/341 and 342 for inputting power installed at one side around the center of the two the source driver integrated circuits 320 and 340 are vertically symmetrical to each other about the centers of the source driver integrated circuits 320 and 340, respectively, and power is supplied to all the pads 321, 322, 341, and 342 from the FPCB 200.
The power supplied from the FPCB 200 via the LOGs 301, 302, 303, and 304 is transferred through metal lines provided in the two source driver integrated circuits 320 and 340. In this case, since the metal line has a line sheet resistance (RL) of a predetermined size, voltage levels of power at two points spaced apart from each other are small, but a predetermined difference exists. Accordingly, the fact that the lengths of the supply paths P11, P12, P13, and P14 are equal to each other represents that an absolute value of power is not known but relative values of the power are equal to each other.
FIG. 1 illustrates only one type of power line as the LOG for the purpose of simplification, but when considering signals and different types of power lines, since an area occupied by the LOG is actually significant, the use of a large number of LOGs may increase the entire size of a device.
In order to solve such a problem, a scheme for reducing the number of LOGs for supplying power has been proposed for use. That is, in the source driver integrated circuits 320 and 340, the pads 321, 322, 341, and 342 for inputting power and the lines are designed for vertical symmetry, but a power source is connected for use only to the pads 321 and 342 for inputting power of the source driver integrated circuits 320 and 340 due to space insufficiency of the LOG lines 301, 302, 303, and 304 in a COG connection.
FIG. 2 illustrates another embodiment of a conventional display device.
Referring to FIG. 2, LOGs 301 and 303 are electrically connected to the two source driver integrated circuits 320 and 340 from FPCB 200, respectively. Accordingly, power is supplied only to one pad 321 of pads 321 and 322 for inputting power installed in the one source driver integrated circuit 320, and power is supplied only to one pad 341 of pads 341 and 342 for inputting power installed in the other source driver integrated circuit 340.
In this case, it can be understood that the lengths of supply paths P21, P22, P23, and P24 of panel driving signals supplied to two channels Chc and Chc+1 or Che and Che+1 are different from each other. That is, the supply paths P21 and P23 of the panel driving signals supplied to one pair of channels Chc and Che of the two pairs of adjacent channels Chc and Che+1, and Che and Che+1 are shorter than the supply paths P22 and P24 of the panel driving signals supplied to the other pair of channels Chc+1 and Che+1.
In this case, since the supply paths P21 and P23 of the panel driving signals are short, a predetermined difference occurs between an image provided by the channels Chc and Che which receive panel driving signals having a relatively high voltage level, and an image provided by the channels Chc+1 and Che+1 which are adjacent to the channels Chc and Che, but receive panel driving signals having a relatively low voltage level.
In other words, when the power source is connected for use only to the pads 321 and 341 for inputting power of the source driver integrated circuits 320 and 340, there is a problem that a right and left pixel image difference of the source driver integrated circuits 320 and 340 and an image difference between the source driver integrated circuits 320 and 340 occur due to resistance deviation of the supply paths P21, P22, P23, and P24 of the panel driving signals, which are arranged at the right and left of the source driver integrated circuits 320 and 340.